The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trench openings typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening through the dielectric interlayer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W) or aluminum (Al). Excess conductive material on the surface of the dielectric interlayer can be removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening in a dielectric layer which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line. In copending application Ser. No. 08/320,516 filed in Oct. 11, 1994 now U.S. Pat. No. 5,635,423, issued Jun. 3, 1997, prior art single and dual damascene techniques are disclosed, in addition to several improved dual damascene techniques for simultaneously forming a conductive line in electrical contact with a conductive plug for greater accuracy in forming fine line patterns with minimal interwiring spacings.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules, e.g., a design rule below about 0.18.mu., the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
Cu and Cu alloys have recently received considerable attention as a replacement material for Al in VLSI interconnection metalizations. Cu has a lower resistivity than Al, and has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
A conventional approach in attempting to form Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Chow et al., U.S. Pat. No. 4,789,648. However, due to Cu diffusion through the dielectric interlayer, Cu interconnect structures are encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium silicide (TiN), titanium tungsten (TiW), tungsten nitride (WN), and silicon nitride (Si.sub.3 N.sub.4) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
In CMP Cu and Cu alloy metalizations, a slurry is typically employed containing a relatively large amount of alumina (Al.sub.2 O.sub.3) e.g. about 2 to about 3 wt. %. However, it was found that the Cu surface undergoes abrasion, i.e. scratching. In addition, conventional slurries for CMP do not exhibit a sufficiently high selectively to the underlying barrier layer and, hence, render it extremely difficult to stop on the underlying barrier layer and achieve a desired degree of ultimate planarization.
Accordingly, there exist a need for a Cu CMP slurry and for a method of CMP Cu metalization which enables high planarization and exhibits high selectivity to an underlying barrier layer.